The present invention relates generally to silicon wafer processing, and more particularly, to devices for holding silicon wafers as they are subjected to ion bombardment and to heat treatment.
Various techniques are known for processing silicon wafers to form devices, such as integrated circuits. One technique includes implanting oxygen ions into a silicon wafer to form buried layer devices known as silicon-on-insulator (SOI) devices. In these devices, a buried insulation layer is formed beneath a thin surface silicon film. These devices have a number of potential advantages over conventional silicon devices (e.g., higher speed performance, higher temperature performance and increased radiation hardness). The lesser volume of electrically active semiconductor material in SOI devices, as compared with bulk silicon devices, tends to reduce parasitic effects such as leakage capacitance, resistance, and radiation sensitivity.
In one known technique, known by the acronym SIMOX, a thin layer of a monocrystalline silicon substrate is separated from the bulk of the substrate by implanting oxygen ions into the substrate to form a buried dielectric layer. This technique of xe2x80x9cseparation by implanted oxygenxe2x80x9d (SIMOX), provides a heterostructure in which a buried silicon dioxide layer serves as a highly effective insulator for surface layer electronic devices.
In the SIMOX process, oxygen ions are implanted into silicon, after which the material is annealed to form the buried silicon dioxide layer or BOX region. The annealing phase redistributes the oxygen ions such that the silicon/silicon dioxide boundaries become more abrupt, thus forming a sharp and well-defined BOX region, and heals damage in the surface silicon layer caused by the ion bombardment.
During the SIMOX process, the wafers are subjected to relatively severe conditions. For example, the wafers are typically heated to temperatures of about 500-600 degrees Celsius during the ion implantation process. Subsequent annealing temperatures are typically greater then 1000 degrees Celsius. In contrast, most conventional ion implantation techniques do not tolerate temperatures greater than 100 degrees Celsius. In addition, the implanted ion dose for SIMOX wafers is in the order of 1xc3x971018 ions per square centimeter, which can be two or three orders of magnitude greater than some known techniques.
Conventional wafer holding devices are often incapable of withstanding the relatively high temperatures associated with SIMOX processing. Furthermore, wafer-holding structures having exposed metal are ill-suited for SIMOX processes because the ion beam will induce sputtering of the metal and, thus, result in wafer contamination. In addition, the structure may deform asymmetrically due to thermal expansion, which can damage the wafer surface and/or edge during high temperature annealing so as to compromise wafer integrity and render it unusable.
Another disadvantage associated with certain known wafer holders is electrical discharge of the wafers. If a wafer holder is formed from electrically insulative materials, the wafer will become charged as it is exposed to the ion beam. The charge build up disrupts the implantation process by stripping the ion beam of space charge neutralizing electrons. The charge built-up on the wafer can also result in a discharge to a nearby structure via an electrical arc, which can also contaminate the wafer or otherwise damage it.
It would, therefore, be desirable to provide a wafer holder that is electrically conductive and is able to withstand the relatively high temperatures and energy levels associated with SIMOX wafer processing while also minimizing the potential for sputter contamination.
The present invention provides a wafer holder assembly that maintains its structural integrity and prevents the build up of electrical charge on the wafer during the ion implantation process. Although the invention is primarily shown and described in conjunction with SIMOX wafer processing, it is understood that the wafer holder assembly has other applications relating to implanting ions into a substrate and to wafer processing in general.
In one aspect of the invention, a wafer holder assembly includes a-structural member that can be mechanically coupled to a target stage within an implanter system. The structural member serves as a base for the wafer holding members and, in one embodiment, can be formed by first and second main structural rails, generally parallel and spaced at a predetermined distance. A first wafer-holding arm rotatably extends from distal ends of the main structural members. In one embodiment, the first arm includes a transverse member having first and second portions, each of which includes a distal tip for releasably engaging a respective wafer-contacting pin. The transverse member is rotatable such that the wafer-contacting pins, which are spaced apart on the wafer edge, apply substantially equal pressure to the wafer.
A second wafer-holding arm extends from a proximal region of the assembly for providing a third contact point on the wafer via a wafer-contacting pin. The second arm pivots about an axis defined by a bearing connected to at least one main structural member to facilitate loading and unloading of the wafer from the assembly. In one embodiment, a bias member biases the second arm towards a wafer-hold position.
In another aspect of the invention, the wafer holder assembly is secured together by a series of retaining members to eliminate the need for conventional fasteners and adhesives, which are associated with wafer contamination. In one embodiment, a distal retainer member includes a first end engageable with the first arm and a second end matable to the main structural members with a spring member extending between the first and second ends. The distal retainer member is held under tension by the spring member so as to secure the first arm to the main structural members while allowing the transverse member to freely rotate about the first axis such that the first and second pins apply equal pressure to the wafer.
An intermediate retainer member can be coupled to the main structural members in an intermediate region of the assembly. In one embodiment, the intermediate retainer member can include first and second opposed U-shaped outer members with a spring member extending therebetween. The spring member is under tension such that the outer members remain engaged with corresponding protrusions on the bottom of the main structural members. The intermediate retaining member maintains the spacing of the first and second main structural members and enhances the overall mechanical strength of the assembly.
The assembly can further include a proximal retainer member disposed in the proximal region of the assembly. The proximal retainer member includes upper and lower members coupled by a proximal spring member. The upper and lower members are engaged to the main structural members by the spring member, which is under tension.
In a further aspect of the invention, the wafer holder assembly provides a conductive path from the wafer to the assembly, which can be coupled to ground. By grounding the wafer, the build up of electrical charge on the wafer is inhibited for preventing potentially damaging electrical arcing from the wafer during the ion implantation process. In an exemplary embodiment, the main structural members, the first and second arms, the bias member, and the retainer members are formed from graphite and the wafer-contacting pins are formed from silicon. These materials provide the necessary rigidity and electrical conductivity for the wafer holder assembly to achieve optimal SIMOX wafer processing conditions. In addition, the likelihood of wafer contamination is reduced since only silicon contacts the silicon wafer and only silicon meets the ion beam, thereby minimizing wafer contamination and particle generation. Further, the graphite bias members have a substantially invariant spring constant over a wide temperature range, such as from room temperature to about 600xc2x0 C. The assembly can, therefore, be substantially calibrated at room temperature.
In yet another aspect of the invention, the wafer-contacting pins have a geometry that is effective to reduce the likelihood of electrical discharges from the wafer. In one embodiment, the pins have a proximal portion for coupling to a distal end of the wafer-holding arms and a distal portion for holding the wafer. In one embodiment, the distal portions have an arcuate wafer-receiving neck disposed between a wedge-shaped upper region and a tapered surface. The geometry of the pin upper region reduces the amount of pin material proximate the wafer so as to reduce the likelihood of electrical arcing between the wafer and the pin during the ion implantation.
In another aspect of the invention, the wafer-contacting pins are coated with a relative hard, conductive material, such as titanium nitride (TiN) or titanium aluminum nitride (TiAlN). The coating provides a durable, abrasion resistant surface for contacting the wafer. In addition, the TiN coating is more conductive than silicon, from which the pin is formed, to enhance electrical contact between the wafer and the pin thereby increasing the amount of current, i.e., charge build up, flowing from the wafer. The TiN coating also prevents so-called wafer-bonding between the wafer and the pin.